Voiceband data set

ABSTRACT

A full duplex, synchronous data set (10) includes primary signal processing circuitry which generates a modulated transmit data signal in response to serial data from a terminal interface (17). The modulated data signal is transmitted over a primary channel of a transmit line (11). The primary signal processing circuitry also receives modulated data signals from a primary channel of a receive line (12) and recovers therefrom a serial bit stream for presentation to the interface. The operating parameters of the primary signal processing circuitry are specified by a primary controller (30) over a plurality of buses (PA, PC, PD). The primary controller includes a microprocessor (310) and associated peripherals (315, 320, 325, 330, 335). The data set also includes secondary signal processing circuitry (40) which transmits and receives diagnostic and control information over respective secondary channels of the transmit line and receive lines. The secondary signal processing circuitry is controlled by a secondry controller (50) over a plurality of buses (SA, SC, SD). The secondary controller also includes a microprocessor (510) and associated peripherals (515, 520, 525, 530, 535). The primary and secondary controllers communicate with each other via a bus interface (60).

BACKGROUND OF THE INVENTION

The present invention relates to the transmission of data and, inparticular, to data sets.

Workers in the data transmission art, particularly in the area ofvoiceband data transmission, have suggested various data set, or modem,designs which, in some way, operate under programmed processor, e.g.,microprocessor, control. Such designs are disclosed, for example, in K.I. Nordling et al, Proceedings 1976 National TelecommunicationsConference, p. 50.2.1 et seq; K. Watanabe et al, Conference Record, 1977International Conference on Communications, p. 47.6-252 et seq; P. J.Van Gerwin et al, IEEE Trans. on Comm., February 1977, p. 238 et seq;U.S. Pat. No. 4,085,449 issued Apr. 18, 1978 to D. M. Walsh et al.

One advantage of incorporating a programmed processor into a data set isthat the design of the data set can be updated relatively inexpensivelyvia program modification both during development of the design and afterfull-scale manufacturing has begun. Another advantage is that the dataset can, with relative ease, be designed to operate with, for example, anumber of signaling rates and modulation formats. Moreover,incorporating a programmed processor into the design makes iteconomically feasible to provide the data set with sophisticatedfeatures, particularly in the area of data set and network diagnostics.

In a number of prior art designs, the real-time signal processing ofuser-provided data and received data signals is performed under programcontrol by the processor itself. In order to ensure that all theprocessing which needs to be done within one symbol interval can becompleted, these designs typically utilize so-called bit-sliceprocessors, at least for high-bit-rate (4800 bit per second or greater)data sets. A drawback of this approach is that bit-slice processors mustbe custom-designed by the data set designer. This adds to the complexityof the design task. Moreover, it requires expertise in such areas ascomputer processor architecture and hardware--areas with which theperson skilled in the data transmission art may not be familiar.

It may be possible to design a data set which is able to perform thenecessary processing using a conventional, e.g., MOS, processor. Adrawback, however, is that substantial programming effort must bedevoted in such a design to keeping real-time transmit and receivefunctions from interfering with one another. Another drawback is that nomatter whether a conventional or bit-slice processor is used, theprocessing capability of the processor may be substantially consumedwith real-time signal processing tasks, leaving little, if any,processor capability for diagnostics or other functions. A potential wayto deal with these drawbacks is to divide the data set functions betweentwo or more processors. There may be difficulty, however, incoordinating their operations.

SUMMARY OF THE INVENTION

In a data set embodying the principles of the present invention, thereal-time processing of user-provided data and/or received data signalsis performed by special-purpose signal processing circuitry. Acontroller, which illustratively includes a programmed processor,controls the signal processing circuitry by providing information as tohow the signal processing circuitry is to perform the real-time signalprocessing. The controller provides this information by writing it intovarious registers within the signal processing circuitry. The registersare individually addressed by the controller to receive informationprovided on a data bus common to all of the registers.

The controller may, more particularly, specify modes of data setoperation, such as modulator state, encoder and decoder signal source,equalizer operating mode, etc. The controller may also specify operatingparameter values, such as carrier frequency, bit rate, and idealreference data to be transmitted during transmitter start-up. It mayalso specify various signal processing formats, such asscrambler/descrambler and differential encoder/decoder algorithms andmodulation formats. The controller does not, however, perform any of thereal-time signal processing of user-provided data or received datasignals.

This separation of control and real-time signal processing functions isadvantageous from at least two standpoints. Since the controller is notrequired to perform the numerous arithmetic operations attendant tohigh-speed data signal processing, a relatively slow, commerciallyavailable microprocessor can be used in the data set, rather than acustom-designed, high-speed, e.g., bit-slice, processor, as mightotherwise be required. Moreover, most of the updating of the data setdesign, once full-scale manufacturing has begun, is likely to be relatedto changes in other than the signal processing per se. Thus, it isadvantageous to allocate the signal processing functions tospecial-purpose circuitry and to retain the flexibility provided by aprogrammed processor principally for off-line (i.e., non-real-time)functions.

The signal processing circuitry is illustratively realized inlarge-scale-integrated (LSI) circuit form. Although the developmentcosts of LSI circuitry is high, its manufacturing costs are relativelylow and, in the long run, a data set comprised of LSI circuits and aconventional processor is, advantageously, more economical tomanufacture than one based on bit-slice processor technology.

The capability of the signal processing circuitry to operate inaccordance with various operating parameter values and signal processingformats is advantageous in that it allows the same signal processingcircuitry and overall data set architecture to be used in a family ofdata sets, i.e., data sets which operate at various speeds and inaccordance with various Bell System, CCITT, or other formats. Thiscapability is also used in the present illustrative embodiment to, forexample, effect the changes in data set operation attendant totransitions between start-ups, normal data transmission and recovery,and turn-offs.

In accordance with a feature of the invention, the controller normallyoperates in a background loop in which it repetitively performs a numberof predetermined background tasks related to the management of off-linedata set operations and the monitoring of both off-line and real-timeoperations. To this end, and also to aid the controller in its controlof the real-time signal processing, the signal processing circuitryillustratively provides information to the controller via a number ofregisters from which the controller can read over the above-mentioneddata bus. The controller controls the real-time signal processing inresponse to interrupts generated by the signal processing circuitry uponthe occurrence of any of several predetermined signal events. Aparticular advantage of this approach is that it provides a way for thecontroller to concurrently control in an orderly way a number of signalprocessing functions, e.g., both start-ups and turn-offs of both thedata set transmitter and receiver circuitry. In particular, uponreceiving an interrupt, the controller suspends its execution of thebackground loop and executes an interrupt service routine which providesto the signal processing circuitry information appropriate to the typeof interrupt that was generated. For example, the signal processingcircuitry generates an interrupt when the so-called request-to-send leadis raised by the user's terminal equipment. This causes the controllerto execute an interrupt service routine which provides informationneeded by the signal processing circuitry to effect a transmitterstart-up.

Two or more interrupt service routines may be associated with aparticular type of interrupt. A feature of the invention is that theparticular interrupt service routine invoked in response to a particulartype of interrupt is determined in the above-mentioned background loop.Thus, when an interrupt is received by the controller, the particularinterrupt service routine to be invoked is already known, therebyminimizing the time required to begin interrupt servicing.

Another feature of the invention is that, as part of the above-mentionedbackground loop, the data set continuously monitors various signalsthroughout the data set to check that it, and the network connected toit, are operating properly.

Another feature of the invention is that at least portions of the signalprocessing circuitry may operate in response to programs which areloaded into the signal processing circuitry by the controller prior tothe initiation of real-time signal processing by those portions of thecircuitry. This feature of the invention further facilitates relativelyinexpensive updating of the data set design.

BRIEF DESCRIPTION OF THE DRAWING

The invention will be clearly understood from a consideration of thefollowing detailed description and accompanying drawing in which:

FIGS. 1-4, when arranged as shown in FIG. 5, show a voiceband data setembodying the principles of the invention;

FIG. 6 shows the division of the bandwidth over which the data setoperates into primary and secondary channels;

FIG. 7 depicts the front panel of the data set;

FIG. 8 shows the overall sequence of operations performed by acontroller within the data set;

FIG. 9 shows various files stored in a read-only memory within the dataset controller;

FIG. 10 shows a task table used by the data set controller;

FIG. 11 depicts a portion of a random access memory within the data setcontroller;

FIG. 12 shows a menu table to which the data set controller refers inexecuting various tests and commands initiated by the data set user;

FIGS. 13-15, when arranged as shown in FIG. 16, show an encoder used inthe data set;

FIGS. 17-19, when arranged as shown in FIG. 20, show a decoder used inthe data set;

FIG. 21 shows a modulator used in the data set; and

FIG. 22 shows a receiver processing and equalization circuit used in thedata set.

DETAILED DESCRIPTION

FIGS. 1-4, when arranged as shown in FIG. 5, depict a full duplex,synchronous data set 10. Data set 10 is illustratively a control dataset connected to a tributary data set of similar design (not shown) viaa four-wire private line comprised of a two-wire transmit line 11 and atwo-wire receive line 12. The bandwidth of both the transmit and receivelines is divided into a primary channel and a secondary channel, asshown in FIG. 6. The primary channel carries modulated data and start-upsignals and also various test signals. The secondary channel carriesdiagnostic and control information between the two data sets.

Data set 10 includes primary and secondary channel circuitries which areassociated with communications over the primary and secondary channels,respectively. In particular, the primary channel circuitry is comprisedof primary signal processing circuit 20, controller 30 and primaryinput/output (I/O) circuitry 80.

Circuitry 20 performs the real-time processing of user-provided data andreceived data signals. As will be described in detail hereinbelow,circuitry 20 receives serial data from the user's terminal equipment(not shown) at 4800 bits per second (bps). This signal is scrambled,encoded and formatted into three-bit symbols. It then modulates acarrier of frequency f_(c) using 8-phase, phase shift keying (PSK),yielding a baud (symbol) rate of 1600. The modulated transmit datasignal is transmitted over the primary channel of line 11. Circuitry 20also receives PSK data signals from the primary channel of line 12,recovers a 4800 bps far-end data stream therefrom and presents it to theuser's terminal equipment. In accordance with the invention, circuitry20 is controlled by controller 30, which provides information tocircuitry 20 as to how the latter is to perform the real-time signalprocessing. Control 30 also controls primary (I/O) circuitry 80. Bothcircuitry 20 and controller 30 operate in response to a clock signal ofapproximately 1.8 MHz provided by primary master clock 25 over lead 26.

The secondary channel circuitry, also referred to as the Data SetDiagnostic Unit (DDU), includes secondary signal processing circuitry40, which is controlled by a secondary controller 50. Controller 50operates in response to a clock signal, also of approximately 1.8 MHz,provided by secondary master clock 45. Circuitry 40 receives diagnosticand control information from controller 50 and converts it into an FSKsignal having upper and lower frequencies f_(U) and f_(L). This signalis transmitted over the secondary channel of line 11. In addition,circuitry 40 receives FSK signals from the secondary channel of line 12and presents a waveform representing the zero crossings of the receivedsignal to controller 50, which recovers the transmitted intelligence.

Controller 50 communicates with controller 30 via a bus interface 60 andcommunicates with a diagnostic control device (DCD) 75 via a diagnosticchannel circuitry 70. Controller 50 also controls secondary I/Ocircuitry 90.

PRIMARY CHANNEL CIRCUITRY--SYSTEM OPERATION Primary Signal Processingand I/O Circuitry

Primary signal processing circuitry 20 interfaces with the user'sterminal equipment via interface connector 17, which is compatible withEIA standard RS-449. Of the interface leads which extend from the user,the SD (send data), TT (terminal timing), and RS (request-to-send) leadsextend via cable 109 through selector 110 to encoder 115 via cable 111.(When the data set is in a digital loopback test mode, selector 110extends to encoder 115 the signals on cable 184 rather than the signalson cable 109.)

The transmitter portion of circuitry 20 is principally comprised ofencoder 115, modulator 120 and D/A converter 125. Encoder 115, inparticular, is a large scale integrated (LSI) circuit which processesthe input data from the SD lead in preparation for modulation. Thisprocessing principally includes the functions of scrambling anddifferential encoding. The encoder output signal passes over cable 116to modulator 120--another LSI circuit. The modulator output on cable 121is a sequence of digital words representing samples of the PSK modulatedsignal to be transmitted. These are passed to D/A converter 125. Theanalog output of the latter on lead 126 is passed through a pad 130 andreleased transfer contact AL-1 of an analog loopback relay AL to oneinput of summing amplifier 15. The other input to the summing amplifieris the output of secondary channel transmitter 415 within secondarysignal processing circuitry 40. The output of summing amplifier 15 isshaped by a transmit low pass filter 14 whence it passes to a compromiseequalizer 13. The latter conditions the outgoing signal to compensatefor some of the expected channel degradation. The output of equalizer 13is extended to transmit line 11.

The received data signal from line 12 is brought into the data setthrough preamplifier 16. The output of the preamplifier extends tosecondary channel processing circuitry 40, as discussed more fullybelow. The output of preamplifier 16 also extends through releasedtransfer contact AL-2 to the receiver portion of circuitry 20.

In particular, the preamplifier output extends to primary channelreceive filter 150. Filter 150 removes the secondary channel signal,passing the primary channel signal to an automatic gain control (AGC)circuit 155. The latter sets the correct levels for proper operation ofthe circuitry which follows.

In particular, the AGC output passes to phase splitter/timing recoverycircuit 160 over lead 156. The timing recovery portion of circuit 160generates a square wave having transitions which correspond to zerocrossings of a baud rate tone extracted from the AGC output signal. Thissquare wave is extended to receiver processing and equalization circuit170 over lead 162 where it is used to control receiver timing. The phasesplitter portion of circuit 160 generates a Hilbert transform signalpair on cable 161 in response to the AGC output signal. The Hilberttransform pair is extended to A/D converter 165 which generates digitalversions of the Hilbert transform signals one after the other in serialform on a lead within cable 166.

Cable 166 extends to receiver processing and equalization circuit 170,which is comprised of several LSI circuits. Circuit 170 performs suchfunctions as adaptive equalization, demodulation and data decisionformation. It presents (presumably correct) decisions as to the valuesof transmitted data symbols to decoder 175 over cable 171. It alsoextends a digital word to AGC 155 over cable 172 specifying the AGCgain.

Cable 172 also carries clock signals for AGC 155. Clock signals are alsoextended to A/D converter 165 over cable 167. Decoder 175, another LSIcircuit, performs the inverse functions of encoder 115, e.g.,differential decoding and de-scrambling. Receive timing and receiverready signals generated by decoder 175 on leads 174 and 182 arerespectively extended to the ones of EIA drivers 185 associated with theRT and RR leads of interface connector 17 via cable 178. In normaloperation the RD (receive data) lead of connector 17, carrying therecovered far-end data, also receives its signal via one of drivers 185from decoder 175. This signal is routed to the driver via decoder outputlead 176, cable 184, selector 110 and lead 112. The ST (send timing)lead of connector 17 receives its signal from encoder 115 via lead 117and another one of EIA drivers 185.

In addition to the receive data signal on lead 176, cable 184 carriesthe receive timing and receiver ready signals from cable 178. Duringdigital loopback tests, the signals on cable 184, rather than thesignals on cable 109, are extended by selector 110 to encoder 115, andselector 110 extends ground potential to the one of EIA drivers 185associated with the RD lead of connector 17.

Other leads of connector 17 include SB (standby), DM (data mode), CS(clear to send), TM (test mode) and SQ (signal quality). These signalsare provided by respective ones of EIA drivers 190 via latches 180 andleads 181. (Another one of latches 180 provides a signal to selector 110via lead 183 indicating whether the data set is to be in the normal ordigital loopback mode.) Further description of the LSI circuits ofcircuitry 20 is given in a separate section hereinbelow.

Primary I/O circuitry 80 includes a set of latches 81. Individual onesof latches 81 control the states of LED indicators 82 disposed on frontpanel 701 of the data set, which is shown in FIG. 7. The two statusindicators are red and green, respectively. The green indicator is onwhen both data set 10 and the far end data set are operating normally;otherwise, the red indicator is on. The DM (data mode) indicator is onif the data set is available to carry user-provided data, as opposed tobeing in a test condition. The TEST CONDITION indicator is on when atest which is disruptive of normal communications over the primarychannel is in progress. (The DM and TM leads of interface 17 are raisedwhen these indicators are on.) The RS, CS and RR indicators show thestate of the corresponding EIA interface leads. The ER indicator is onwhen data set equalizer is in a retrain mode. (SD and RD indicators 89of panel 701 are driven directly from the corresponding EIA interfaceleads via buffers not shown. Diagnostic channel indicator 94 iscontrolled by secondary channel circuitry.)

Other ones of latches 81 control various relays in the data set, such asanalog loopback relay and a select standby relay SR.

I/O circuitry 80 also includes a set of buffers 84 through which thepositions of various front panel switches 85 can be read. These areoperated by the user to issue commands to the data set and to requestthat it perform various tests on itself and/or the network to which itis connected. Other ones of switches 85 (not shown in the drawing)define a local address for the data set. When diagnostic control device(DCD) 75 is associated with a number of data sets co-located with dataset 10, this local address provides the DCD with a way of directing itscommunications to data set 10. In addition, signals from bus interface60 can also be read through ones of buffers 84.

I/O circuitry 80 also includes a four-character alpha-numeric display87. When data set or network faults are detected, the display is used toindicate their nature to the user. In addition, the data set usesdisplay 87 to present mnemonics for the tests and commands which theuser can order the data set to execute. It also uses the display topresent test results, for example, in the form of a word (PASS) or ameasurement (03 DB).

Primary Controller

Primary controller 30 includes a microprocessor 310 and associatedperipherals including read only memory (ROM) 315, random access memory(RAM) 320, timer circuitry 325, interrupt controller 330 and chip selectdecoder 335. Controller 30 communicates with its peripherals and therest of the data set by writing information into, and readinginformation out of, registers, buffers and/or latches throughout thedata set. This communication is carried out via three buses--primaryaddress bus PA, primary control bus PC, primary data bus PD--and aprimary chip select cable PCS.

The leads 336 of cable PCS are derived by chip select decoder 335 from asubset of the address bus leads. The leads of cable PCS extend tovarious integrated circuit chips or groups of chips (e.g., ROM 315)within the data set. When it is desired to communicate with a particulardevice, i.e., register, buffer or latch, microprocessor 310 provides onbus PA an address unique thereto. Decoder 335 provides a signal on anappropriate one of leads 336 indicating that the controller wishes tocommunicate with the device in question. If more than one device isassociated with a particular chip select lead, the particular circuitdesired to be communicated with is identified by an address on bus PA.

Data bus PD is a bidirectional 8-bit bus over which the informationitself is carried. Control bus is a two-bit bus having a read lead and awrite lead. Activation of the write lead means that information providedon bus PD is to be written in a register or latch which has beenaddressed. Activation of the read lead means that information is to beprovided on bus PD by the register or buffer which has been addressed.

Not all leads of all buses extend to each circuit with which controller30 communicates. For example, latches (buffers) receive only the write(read) lead of the control bus. In addition, the various integratedcircuits comprising the data set may receive less than the full numberof address leads, depending on the number of addressable elementscontained therein.

Some of the functional blocks shown in FIGS. 1-4, e.g., latches 81 andbus interface 60, receive more than one chip select lead, as indicatedby a cable, rather than a lead, tap off of chip select cable PSC.Buffers used to drive the three buses and cable PSC are not shown in thedrawing.

The overall operation of controller 30 in accordance with a feature ofthe invention is depicted in FIG. 8. Firstly, controller 30 initializesitself and the rest of the data set. It then enters a background loop inwhich it repetitively performs a number of predetermined background"tasks" related to the management and monitoring of off-line data setoperations and the monitoring of both off-line and real-time operations.(One pass through the background loop requires about 15 ms.) Operationsof the controller which relate to the control of the real-time signalprocessing (as well as some other operations) are handled on aninterrupt basis. Interrupts are generated, for example, in response tovarious signal events within circuitry 20. As a particular example, aninterrupt is generated by encoder 115 when the RS (request-to-send) leadis raised by the user's terminal equipment. The reception of aninterrupt causes controller 30 to suspend its execution of thebackground loop and to service the interrupt via an appropriateinterrupt service routine.

The interrupt service routine causes controller 30 to write intorespective registers of circuitry 20 various operating mode, operatingparameter and/or signal format information signal values appropriate tothe type of interrupt generated. For example, in the case of aninterrupt generated by a raising of the RS lead, controller 30 performsoperations such as configuring encoder 115 for start-up, turning onmodulator 120, loading (jamming) ideal reference (start-up) data intoencoder 115, configuring encoder 115 for normal operation, and raisingthe CS (clear-to-send) lead.

Once an interrupt service routine (or any phase thereof which isseparated from the following phase by a significant times interval) iscompleted, controller 30 returns to the background loop at the placewhere it left.

The various programs, routines and data files used by controller 30 incarrying out the above-described three functions are stored inindividual files within ROM 315. As shown in FIG. 9, these files can beconceptually divided into seven categories--background diagnostics file901, communication control files 911 and 912, DDU file 921, EIA files931 and 932, modem operational files 941-943, test and command files951-953 and utility files 961-965.

Each of the first six file categories includes one or more file types.For example, several of the categories include utility routines. Theseroutines define operations which are common to at least two otherroutines within that category and are called by these other routines, asneeded. In a similar vein, general utility routines 965 defineoperations which are common the routines in various of the categories.The functions of the other file types are explained at appropriatepoints in the sequel.

Overall control of the three basic functions of controller30--initialization, background loop, and interrupt servicing--isprovided by files within the utility category, these beinginitialization routines 963, task handler 961 and interrupt handler 962.The operation of each of these will now be described.

Primary Controller Operation--Initialization/Background Loop

Controller 30 is controlled by initialization routines 963 when power isapplied to the data set. During initialization, various pointers withinthe microprocessor are set and various registers within themicroprocessor are cleared. Latches, such as latches 180, are set topredetermined (e.g., cleared) states. In addition, numerous operatingmode signals held in registers within the data set--principally withincircuitry 20--are set to predetermined initial values. These include,for example, a signal which specifies the state (on or off) of themodulator, signals which specify the signal sources for the encoder anddecoder, signals which specify various operating modes for theequalizer, etc.

A further initialization function is to specify various operatingparameter values and signal processing formats for the LSI circuits ofcircuitry 20. Although data set 10 operates with 8-phase PSK havingpredetermined differential encoding and scrambling, predeterminedcarrier frequency, predetermined start-up protocols, etc., a feature ofthe present invention is that circuitry 20 is capable of operating inaccordance with various operating parameters and signal processingformats. For example, modulator 120 is capable of implementing (a) phaseshift keying (PSK) using 100 percent excess bandwidth at 1200 baud, (b)PSK using 50 percent excess bandwidth at 1600 baud and (c) quadratureamplitude modulation (QAM) using 12 percent excess bandwidth at 2400baud. It can operate over a wide range of carrier frequency. Encoder 115is capable of implementing any of a number of scrambling anddifferential encoding algorithms and QAM signal constellations. Receiverprocessing and equalization circuit 170 and decoder 175 are similarlyflexible.

At this time, then, the encoder and decoder receive information as tothe scrambling/descrambling and differential encoding/decodingalgorithms to be initially used, i.e., during transmitter and receiverstart-up. These may be changed later as, for example, when transition ismade from transmitter start-up to normal transmitter operation.Modulator 120 and receiver processing and equalization circuit 170receive information as to which of the three above-mentioned modulationformats are to be used (in this case, format (b)) and also what thecarrier frequency is--illustratively 1800 Hz.

Various random access memories are also loaded by initializationroutines 963. These include random access memories within encoder 115and decoder 175 which hold microcoded program instructions under thecontrol of which the encoder and decoder operate. Also initialized areall of the numerous variables stored in RAM 320, a number of which,shown in FIG. 11, are discussed below.

When the initialization routines have all been executed, controltransfers to task handler 961. This routine carries out the backgroundloop, causing controller 30 to sequentially perform the above-mentionedbackground tasks. Each task is defined by a set of instructionsindicating what the controller is to do in performing the task.

Task handler 961 operates in conjunction with a task table 1001 shown inFIG. 10. The status and count columns of the table are contained withinRAM 320; the function column is contained within data file 964 of ROM315. Each line entry in table 1001 represents a different task, and thetask handler considers each task in turn. If the status of the task is"active", control is transferred to that location in ROM 315 where thetask is stored, and the task is performed. (The symbol "&" used in FIG.10 means "address of.") If the status of the task is "suspend," or"wait," the task is not performed; the task handler simply goes on tothe next task. (A task may be placed in the "suspend" status, forexample, if its execution would interfere with other data setoperations. An example of placing a task in the "wait" status is givenbelow.) When the last task in the table has been completed, task handler961 returns to the first task and so forth.

As seen in FIG. 9 each ROM file category, except the utility category,includes one or more tasks. Typical tasks in each category will now bedescribed.

The background diagnostic task 901, comprising the entire backgrounddiagnostic file, continually checks the integrity of the data setcircuitry, in accordance with a feature of the invention. For example,various data patterns are read into and out of RAM 320 to ensure thatdata can, in fact, be accurately read in and out of the RAM. The voltageof a standby battery (not shown) for RAM 320 is checked. The sum of thecontents of each of the chips comprising ROM 315 is formed and comparedto a known value to ensure that the proper chips where inserted in theproper places during data set manufacture and to ensure that the ROMcontents remain correct.

Another aspect of the background diagnostic task is to read an ID wordstored in a particular register in each of the LSI circuits of circuitry20. The value of each ID word, as read, is compared to the known valuethereof stored in ROM 315. The ability of controller 30 to retrieve theproper ID word from each LSI circuit is a good indication that at leasta considerable portion of the controller 30 bus structure is functioningproperly. It is also one indication that the LSI circuits are themselvesoperational and that the proper LSI circuit was inserted in the properplace during data set manufacture.

The background diagnostic task also monitors the peak signal level ofthe modulator 120 output signal to assure that it is within operationallimits. It also examines the value of (sin² θ+cos² θ) (θ being thecarrier angle), which is computed and held in receiver processing andequalization circuit 170. That value should always be equal to unity.Verification that it is, in fact, equal to unity is a good indicationthat circuit 170 is functioning properly. Upon the failure of any ofthese diagnostic checks, the background diagnostic task sets a flag in adata set health word 1101 stored in RAM 320, as shown in FIG. 11.Through the operation of other tasks, as described more fullyhereinbelow, the finding of a fault and the resulting setting of anappropriate flag in health word 1101 causes front panel statusindicators 82 to be switched to red on/green off and a mnemonic for thefault is presented on display 87.

The modem operational task 941 is principally comprised of a number ofso-called consistency checks. For example, the state of the RS(request-to-send) lead, which can be read from encoder 115, is comparedwith a transmitter status word 1104 within RAM 320. The transmitterstatus word indicates whether the transmitter circuitry is, for example,off, on, in start-up, or in turn-off. If the RS lead and transmitterstatus word are inconsistent, the controller initiates a transmitterturn-on or turn-off in accordance with the RS lead signal. In similarfashion, a signal within receiver processing and equalization circuit170 indicating the presence of received signal energy is compared to areceiver status word 1108 within RAM 320. Again, if there is aninconsistency, a turn-on or turn-off of the receiver circuitry isinitiated. The modem operational task also performs a streaming check ifthe data set has been optioned for same. In accordance with this check,the time over which the RS lead remains high is monitored. If it exceedsa predetermined value, the task turns off the modulator and sets a flagin health word 1101, again resulting in an indication of the fault onfront panel 701.

EIA tasks 931 involve the monitoring of various leads to which the dataset is connected. One EIA task monitors the status of various leads ofEIA interface connector 17, which it stores in an EIA states word 1112,and upon detecting transitions, takes appropriate action. For example,upon detecting via one of EIA buffers 105 that the LL (local loopback)or RL (remote loopback) lead has been raised by the user's terminalequipment, this EIA task invokes an appropriate one of EIA tests 932,which runs the test. Similarly, upon detecting via another one ofbuffers 105 that the SS (select standby) lead has been raised, this taskcauses relay SR to close. The resulting closure of relay contact SRindicates to back-up circuitry associated with the data set 10 that thelatter is to be connected to a back-up transmission channel. The SB leadis also raised at this time, indicating that the back-up channel is inuse.

In accordance with another EIA task, the states of various leads ofinterface 17 are sampled over successive five-second intervals. If allsamples of a particular lead show that lead to have been off (on)throughout a given interval, an "off" ("on") state indication is storedfor the lead. If it changes state during the interval, a "changing"status indication is stored. The ensemble of status indications, storedas a word 1114, is reported to DCD 75 in response to a request for same.

Tests and commands tasks 951 include, for example, so-called facilityhealth monitoring. A typical facility health monitoring function is tomonitor an RSQ (received signal quality) word 1119 which is generatedwithin the data set and which reflects the average received signalconstellation dispersion. If the RSQ word crosses a predeterminedthreshold, indicating a likelihood of a high data decision error rate, afacility failure flag within health word 1101 is set. Another facilityhealth monitoring function is the monitoring of the received signallevel. A determination that that level is too high or too low also setsa flag in health word 1101.

The communication control tasks relate to communications between thedata set and the user, including, for example, the scanning of switches85, activation of status indicators 82 and the control of display 87.Another communication control task is a so-called test manager whichoversees the running of data set and network tests.

A more detailed discussion of operation of these tasks is included inthe COMMANDS AND TESTS section below. A discussion of DDU handler task921, via which controller 30 communicates with controller 50, is alsoincluded in the discussion.

Primary Controller Operation--Interrupts

As previously mentioned, execution of the background loop via taskhandler 961 continues indefinitely until controller 30 receives aninterrupt. Within the controller, interrupts are received bymicroprocessor 310 via lead 331. In accordance with a feature of theinvention interrupts originate from several places within circuitry 20and are generated in response to various signal events within thatcircuitry. The previously mentioned request-to-send interrupt, forexample, is generated by encoder 115 on lead 118 when the user'sterminal equipment raises or lowers the RS lead. Receiver processing andequalization circuit 170 generates an energy detect (COV) interrupt onlead 173 when signal energy appears on, or disappears from, cable 166.Decoder 175 generates a word trap match interrupt on lead 177 when aparticular received data word, such as a synchronization word, isdetermined to have been received.

In addition, interrupts are generated on leads 326 by respective ones ofthree timers 325a, 325b and 325c within timer circuitry 325. Each ofthese timers is programmed by microprocessor 310 to operate principallyin one of two modes. In the so-called divide-by-N mode, the timer willgenerate an interrupt for every N pulses from a respective clock signal,where N is a number specified by the microprocessor over data bus PD. Ina monostable mode, the timer provides a single interrupt after apredetermined number of clock pulses (again specified by themicroprocessor) have occurred. Timers 325a and 325b are used principallyin connection with transmitter and receiver operations, respectively.Timer 325c is a general purpose timer used, for example, in connectionwith tests and with the decrementing of the task table "wait" statuscount, as described below. Although not shown in the drawing, timers325a, 325b and 325c respectively receive their clock signals fromencoder lead LSC, one of decoder leaders 1918 and encoder lead NDR,which leads are discussed below.

When microprocessor 310 receives an interrupt from interrupt controller330 over lead 331, control transfers from task handler 961 to a utilityroutine referred to as interrupt handler 962. The principal job of thelatter is to determine the source of the interrupt by interrogatinginterrupt controller 330 and to then transfer control to an appropriateone of interrupt service routines 942 (a set of modem operational files)of interrupt service routines stored in other files of ROM 315.

Two or more interrupt service routines 942 are associated with sometypes of interrupts, such as the request-to-send and energy detectinterrupts. For example, one request-to-send interrupt service routineis to be invoked when the data set is optioned for continuous carriertransmission, and a different one is to be invoked if the data set isoptioned for switched carrier transmission. In accordance with a featureof the invention, the particular interrupt service routine to whichcontrol is to be transferred in response to a particular type ofinterrupt is determined in the background by, for example, the one oftests and commands tasks 951 referred to as the test manager (describedbelow). The starting address of that routine is stored in an interruptpointer--a particular location in RAM 320 associated with the type ofinterrupt in question. RAM 320 thus includes request-to-send, energydetect (COV) and word trap match interrupt pointers 1125, 1127 and 1129,respectively, and timers 325a, 325b and 325c interrupt pointers 1131,1133 and 1135, respectively. Upon determining from interrupt controller330 what type of interrupt was received, interrupt handler 962 reads theappropriate interrupt pointer and transfers control to the addressstored therein.

By way of example, a detailed description of the operations performed bycontroller 30 in servicing a request-to-send interrupt will now begiven.

The first operation of the routine is to determine from encoder 115 thestate of the RS (request-to-send) lead. This is necessary because arequest-to-send interrupt is generated both when the RS lead is raisedby the user's terminal equipment and when it is dropped and differentoperations are to be performed, depending on which of these hasoccurred. For the present example, it is assumed that the RS lead hasbeen raised, indicating that the terminal equipment has data which itwishes to transmit.

The request-to-send interrupt service routine then enters its firstphase. In this phase, it first sets timer 325a to a divide-by-N modesuch that interrupts will be generated by the timer every other symbolinterval in alignment with the baud clock which is generated by encoder115 and which is readable by controller 30 over the data bus. Inaddition, the starting address of the next phase of the routine, whichis to be executed when 325a timer generates its next interrupt, isstored in timer 325a interrupt pointer 1131. In addition, the RSindicator on front panel 701 is turned on via the corresponding one oflatches 81.

Further operations in the first phase include writing information intovarious registers within encoder 115 and modulator 120. This includes,for example, setting a bit in the modulator indicating that themodulator is to be on. In addition, information is written into encoder115 to indicate that ideal reference (start-up) data (which is to beencoded and passed on to modulator 120 during start-up) will be beingloaded into encoder 115 every other symbol interval, with idealreference data for two symbol intervals being loaded each time. Indeed,ideal reference data for the first two start-up symbol intervals wasalready loaded into encoder 115 as part of the most recently executedtransmitter turn-off routine. (Other information loaded into the encoderby the turn-off routine includes information relating to thedifferential encoding algorithm to be used during start-up, and aprogram counter word indicating the address within the encoder RAM ofthe program which defines the order of operations to be performed by theencoder during start-up).

Information is also loaded into encoder 115 which inhibits operation ofthe initial portion of the scrambler circuit--the so-calledprescrambler. In addition, certain variables are set up in RAM 320. Forexample, transmitter status flags 1104 is set to indicate that the dataset is, in fact, in transmitter start-up; a start-up pointer 1141 is setto the address in ROM 315 which holds the ideal reference data for thenext two symbol intervals; a start-up counter 1143 is initialized to acount equal to the number of times the ideal reference data loadingoperation is to be performed. The routine then returns control tointerrupt handler 962 which, in turn, transfers control back to thebackground loop.

The ideal reference data previously loaded into encoder 115 is encodedand transmitted by encoder 115 and modulator 120 during the next twosymbol intervals. Timer 325a thereafter times out, thereby generating aninterrupt and invoking interrupt handler 962. The latter reads interruptpointer 1131 (since timer 325a was the source of the interrupt) andtransfers control to the next phase of the interrupt service routine. Atthis time, the routine reads start-up pointer 1141; reads from the ROMlocation whose address is stored in the start-up pointer the idealreference data for the next two symbol intervals; loads that data intoencoder 115; increments start-up pointer 1141 so that it points to thenext ideal reference word; decrements start-up counter 1143 and thenexamines the contents of the counter. Assuming that the start-up countervalue is non-zero, the routine again returns control to interrupthandler 962 and thence to the background. Timer 325a generates aninterrupt two symbol intervals later and the process repeats.

When the contents of start-up counter 1143 are found to be zero, timer325a interrupt pointer 1131 is set to the address of the next phase ofthe routine and return is made to the interrupt handler only after theoperation of timer 325a is modified to time a 12-baud interval. Thestructure of timer circuitry 325 is such that before timing the 12-baudinterval, timer 325a will operate for one more cycle in accordance withits previous mode of operation. Thus, two symbol intervals later, timer325a generates another interrupt, and control transfers to the nextphase of the interrupt service routine. In this phase, information isloaded into encoder 115 indicating that scrambled marks must now betransmitted by clamping the SD (send data) lead low. In addition, theencoder program counter is now set to that portion of the encodermicrocode defining the order of operations for normal, transmitter on,operation. Information indicating the type of differential encoding tobe used during normal, as opposed to start-up, operation is alsocommunicated to the encoder. Control is then returned to task handler962 and thence to the background. In addition, timer interrupt pointer1131 is set to the address of the last phase of the routine.

Twelve symbol intervals later, timer 325a generates its last interrupt,and control transfers to the last phase of the routine. At this time theSD lead is unclamped; the prescrambler is enabled; the CS(clear-to-send) lead is raised; the CS (clear-to-send) indicator 82 isturned on; transmitter status word 1104 is set to indicate "transmitteron"; and timer 325a is turned off.

The interrupt service routines associated with the energy detect andword trap match interrupts are similarly comprised of instructions whichimplement the appropriate data set operations for the interrupt inquestion. For example, an energy detect interrupt generated by circuit170 upon the detection of energy on the signal lead within cable 166initiates a receiver start-up via an interrupt service routine which isexecuted in phases in response to interrupts from timer 325b. In theinitial phase, controller 30 configures circuit 170, for example, to usean initial timing recovery mode, AGC adaption step size and set ofequalizer coefficient values. In addition, a bit is set in circuit 170to indicate that ideal reference data (which is used in initialequalizer training) will be being jammed from controller 30. At thistime, decoder 175 is configured to perform the inverse of the initialstart-up operations of encoder 115.

As the receiver start-up continues, the interrupt service routinedirects such functions as the actual jamming of ideal reference data,changing the AGC step size and enabling the carrier recovery circuit. Atthe end of the start-up, the RR (receiver ready) and SQ (signal quality)leads are raised. (The SQ lead follows the RR lead except that theformer is low when the equalizer within circuit 170 is in a retrainmode.) At this time, in addition, the RR indicator on panel 701 isturned on and the RD (receive data) lead--which was previously clampedlow--is unclamped.

The word trap match interrupt is used in the course of various, e.g.,end-to-end, tests. The principal job of its associated interrupt serviceroutine is to initiate the first phase of various routines which takeadvantage of the word trap capability of the data set.

Interrupts generated by timer 325c, for example, are used in connectionwith the "wait" status of tasks in task table 1001. In typical data setoperation, this timer is operated in the divide-by-N mode. Itsassociated interrupt pointer 1135 is set to the address of an interruptsevice routine which decrements the count associated with each taskhaving the "wait" status. When a count is found to be zero, theinterrupt service routine changes the status of the task to "active," sothat the task is executed in the next pass through the task table. Partof the task may be to return its own status to "wait" and to reset theassociated count to an initial value. In this way, the task is executedperiodically, but not in every pass through the task table. The statusreporting task described below is an example of this type of task.

PRIMARY CHANNEL CIRCUITRY--LSI CIRCUITS General

As previously noted, each of the LSI circuits of circuitry 20--encoder115, modulator 120, receiver processing and equalization circuit 170(which is illustratively comprised of four separate LSI circuits) anddecoder 175--is designed to operate in data sets employing differentscrambling and differential encoding algorithms, bit and baud rates,modulation formats, carrier frequencies, etc. These circuits, moreover,can be used in data sets which operate over the switched telephonenetwork or private line networks. The latter include both point-to-pointand multipoint (polling) networks and both extended and nonextendednetworks. The encoder and decoder circuits, moreover, includearrangements which allow up to four 2400 bps data signals to bemultiplexed at the transmitting end, transmitted at 9600 bps anddemultiplexed at the receiving end.

Data set 10 operates on a point-to-point, nonextended private line on anonmultiplexed basis. It uses 8-phase PSK. In order to simplify theensuring description, circuitry within the LSI circuits which is notrequired to effect this mode of operation for data set 10, is not shownor described herein. Thus, circuitry relating to the following, forexample, is not discussed: multiplexing and demultiplexing; multipointpolling; the generation of QAM constellations; elastic data storage(which is used in extended networks).

All three primary buses, address bus PA, control bus PC and data bus PD,as well as a respective lead from chip select cable PCS, extend to eachLSI circuit (or in the case of circuitry 170 one of the LSI circuitstherein). As shown in the FIGS. which depict the LSI circuits, bus PDextends directly to and from each of the LSI circuit registers withwhich controller 30 communicates. For purposes of drawing simplicity,the FIGS. do not show controller interface circuitry, to which buses PAand PC and the chip select lead extend in each LSI circuit interface.(The chip select extending to the encoder, modulator, receiverprocessing and equalization circuit, and decoder are designated CS1,CS2, CS3 and CS4, respectively.) This circuitry, however, is ofconventional design. It responds to an enable signal on the chip selectlead to operate the register whose address is then on bus PA. Inparticular, the controller interface circuitry causes information to bewritten into the register from bus PD when the write lead of control busPC is enabled and causes information to be read from the register ontobus PD when the read lead of bus PC is enabled.

In a similar vein, it is to be noted that most of the LSI circuitregisters which communicate with controller 30 are capable of holdingeight bits of information. For the most part, the function of those bitswhich do not relate to the operation of data set 10, as configured, are,again, not discussed herein.

Encoder

FIGS. 13-15, when arranged as shown in FIG. 16, depict encoder 115. ThisLSI circuit is comprised of a clock generator 1580 and five signalprocessing modules--terminal interface 1310, health module 1340,scrambler 1440, differential encoder 1460 and modulator interface 1540.The signal processing modules are controlled by a controller 1410.

Data from controller 1410 is carried to modules 1340, 1440, 1460 and1540 via encoder outbound data bus EOB. Data is received from modules1310, 1340, 1440 and 1460 via an encoder inbound data bus EIB.Individual select leads are extended from controller 1410 to each othermodule via encoder select cable ES, with two select leads going tohealth module 1340 and one to each of the others. In addition,controller 1410 provides clock signals to health module 1340, scrambler1440 and differential encoder 1460 over encoder clock lead EC.

At the beginning of each transmitter baud interval, controller 1410accesses, i.e., enables the select lead of, terminal interface 1310. Thelatter, in response, provides on bus EIB a four-bit word comprised ofdata bits provided either by the user or generated within the data set.(Since data set 10 transmits three bits per baud, only three of the fourbits on the four-bit word will have been derived from the user, thefourth bit being a "don't-care" bit.) Controller 1410 thereafteraccesses modules 1340, 1440 and 1460 in a predetermined sequence. Aseach module is accessed, it reads from bus EOB the four-bit wordpreviously stored in controller 1410. The module processes that word inresponse to clock pulses on lead EC and returns the processed word tocontroller 1410 over bus EIB. When the desired processing has beencompleted, controller 1410 accesses modulator interface 1540, whichreads in the processed four-bit word from bus EOB and extends it inserial form to modulator 120 over lead SDA--one of the leads of cable116.

Controller 1410 includes RAM/program counter (hereinafter referred to asRAM) 1426, control logic 1422, interface 1431, and registers 1411, 1414,1417 and 1419. During data set initialization, controller 30 sets aconfigure but in register 1414 indicating that controller 1410 is to bein a configure mode. This bit, as well as three other bits of register1414, is extended to control logic 1422. The latter, which receives theclock signal from primary master clock 25 over lead 26, responds to theset state of the configure bit by extending a signal to RAM 1426 over alead of cable 1423, indicating that the RAM is to load successiveprogram instructions placed in register 1419 by controller 30 into theRAM location placed by controller 30 in register 1417. Both registers1417 and 1419 are operated in an unbuffered mode at this time. That is,whenever information is loaded into them, it passes immediately to RAM1426.

The instructions loaded into RAM 1426 represent a number of programs,each defining the order of operations to be performed within encoder 115for different modes of encoder operation, e.g., transmitter start-up,normal data transmission, etc. Once the initialization of controller1410 is complete, controller 30 clears the configure bit in register1414 and writes into register 1417 the address of the first instructionof the program in RAM 1426 which governs encoder operation duringtransmitter start-up. This address is loaded into the program counter ofRAM 1426.

When encoder 115 is to begin encoding, controller 30 sets an operatingmode, run, bit within register 1414. The start of each baud interval issignaled to control logic 1422 via a 1600 Hz baud clock provided byclock generator 1580 over transmitter baud clock lead TBD. At thebeginning of the next transmitter baud interval, control logic 1422begins pulsing RAM 1426 over another lead of cable 1423, causing theprogram counter to increment, whereby successive instructions of theprogram being run are provided back to control logic 1422 over cable1427. Each of these instructions includes two pieces of information--themodule to be accessed and the number of clock pulses (from one to four)to be generated on lead EC. This information is decoded by the controllogic, which enables the appropriate lead in select cable ES andgenerates the specified number of clocks on lead EC. Control logic 1422also pulses interface 1431 over cable 1424 to control the flow offour-bit words from bus EIB and onto bus EOB.

The completion of the processing for a given baud interval is manifestedto control logic 1422 via a so-called halt instruction in the program.Control logic 1422 responds thereto by (a) terminating the incrementingof the program counter and (b) signaling RAM 1426 to read into itsprogram counter an operating mode signal in the form of an address inregister 1417. That address is the address of the first instruction ofthe next program to be run. As long as the encoder is in a particularoperational mode, e.g., transmitter start-up, that address will be thesame as was loaded into the program counter at the start of the previousbaud interval.

Except during initialization, register 1417 is operated as a doublebuffered register. This means that the register is comprised of twosections--an outside section and an inside section. Information fromcontroller 30 is written into the outside section but controller 1410operates in response to information in the inside section. Thisarrangement allows controller 30 to write the starting address of a newRAM program to be executed without disturbing the current operation ofcontroller 1410 and without the controller having to keep track of wherethe encoder is in its processing cycle. When it is desired to effect atransfer of information from the outside section to the inside sectionof the register, controller 30 clears a previously-set register writebit stored in register 1414. This is responded to by control logic 1422at the beginning of the next baud interval by extending a transfer pulseto register 1417 (via a lead not shown), effecting the transfer ofwhatever information is in the outside section of the register into theinside section thereof.

Other registers (identified hereinbelow) which controller 30 writes intoare double buffered. These registers also receive the transfer pulsefrom control logic 1422.

The values of the four bits in register 1414 (one of which is describedbelow) are extended not only to control logic 1422 but also to monitorregister 1411 from which they can be read by controller 30 in order toverify that their values are correct. Register 1411 also holds thepreviously-described ID word for the encoder.

Terminal interface 1310 receives the request-to-send and send datasignals from the RS and SD leads of EIA interface connector 17 via cable109, selector 110 and cable 111. (Although the input leads to thismodule are not actually the RS and SD leads of the interface connector,they are labeled as such in FIG. 13 to help the reader follow the signalflow.)

The request-to-send signal is received by a clamp and invert circuit1317 which, as a function of the states of two operating mode bits indouble-buffered register 1311, clamps the request-to-send signal,inverts it, or passes it through unchanged. The output of circuit 1317extends to transition detector 1319, an output of which isrequest-to-send interrupt lead 118. The state of the request-to-sendsignal is monitored by controller 30 via a bit in monitor register 1314.Another bit in that register is controlled by transition detector 1319over lead 1320; that bit is set for one baud interval following arequest-to-send transition and is thereafter cleared. To this end,detector 1319 receives the baud clock on lead TBD.

The send data signal is received by data input circuit 1331. Thiscircuit also receives serial bit streams from pseudo-random word (PRW)generator 1339 over lead 1340 and from jam data buffer 1328 over lead1329. The jam data buffer includes an 8-bit register and associatedcontrol circuitry.

The operation of circuit 1331, buffer 1328 and generator 1339 iscontrolled by information in doble-buffered register 1322. Inparticular, two operating mode bits in register 1322, provided on cable1324, determine whether circuit 1331 will take as its input signaluser-provided data from the SD lead, ideal reference or other data frombuffer 1328 (loaded into the buffer from controller 30) or apseudo-random word from generator 1339, the latter being used as part ofcertain tests. Another two bits from this register extend to generator1339 via cable 1326. One of them indicates whether a 15- or 511-bit wordis to be applied to circuit 1331. The other bit causes generator 1339 toinject a single bit error in the pseudo-random word (so that theerror-detecting capability of the far end data set can be tested).Another bit of register 1322 extends to buffer 1328 via lead 1323. Thisbit is always in the set state in data set 10 and indicates to thebuffer that it is to operate in a parallel-to-serial mode.

The output of circuit 1331 extends to data clamp/invert circuit 1334which provides a similar function to circuit 1317 and which iscontrolled by two operating mode bits in double-buffered register 1325.The output of circuit 1334 is extended to serial/parallel (S/P)converter 1337 which provides the data in parallel form onto bus EIBwhen terminal interface 1310 is accessed. Circuits 1331 and 1337, buffer1328 and generator 1339 all receive from clock generator 1580 a 4800 Hzbit clock via transmitter bit clock lead TBT.

Two signals from terminal interface 1310 are extended via cable 1336 tomonitor register 1589 in clock generator 1580 where they can bemonitored by controller 30. One of these is a signal from buffer 1328 onlead 1330 indicating when it is empty and thus able to accept new data.The other is a tap off of the output of circuit 1334 on lead 1335.

Health module 1340 is essentially comprised of a health monitor register1344. The function of this module is to store four-bit words generatedby the other modules in the course of the encoding process. Eachfour-bit half of register 1344 has its own select lead in cable ES. Thuseach half can be accessed independently by controller 1410 to store arespective four-bit word. The words stored in register 1344 are examinedby controller 30 to check that the encoder and its various elements areoperating properly. If, for example, the two halves of register 1344 arerespectively accessed by controller 1410 before and after scrambler 1440is accessed, the two words stored in register 1344 will be the scramblerinput and output. These can be compared by controller 30 to verify thatthe scrambler is operating properly.

Register 1344 is the only encoder register read by controller 30 whichis double buffered. As long as a register read bit in register 1414 isset, there is no transfer of information from the inside section ofregister 1344 to its outside section. When the register read bit iscleared, however, this register, like the other double-bufferedregisters, receives a pulse from control logic 1422 (via a lead notshown) at the beginning of each baud interval to effect the transfer.

Scrambler module 1440 is comprised of a programmable scrambler circuit1441 and double-buffered register 1444. Programmable scrambler circuit1441 includes the circuitry necessary to implement a number of CCITT andBell System scrambling algorithms. Four signal processing format bitsfrom register 1444, extended to circuit 1441 over cable 1445, indicatewhich scrambling algorithm will be used and also provide scramblerclearing.

Differential encoder module 1460 is comprised of a programmabledifferential encoder circuit 1461 and a double-buffered register 1464.Programmable differential encoder circuit 1461 includes the circuitrynecessary to implement a number of CCITT and Bell System differentialencoding algorithms. Four signal processing bits from register 1464,extended to circuit 1461 over cable 1465, indicate which differentialencoding algorithm will be used and also provide differential encoderclearing.

Modulator interface module 1540 includes parallel/serial (P/S) converter1544, new data ready (NDR) clock 1548 and a monitor register 1541. Ineach baud interval, converter 1544 receives from controller 1410 on busEOB a four-bit word representing the phase to be imparted to thetransmitted carrier by modulator 120. At the start of the next baudinterval, while terminal interface 1310 is providing to controller 1410the next four-bit word to be encoded, modulator interface 1540 shiftsthe four bits theretofore loaded into it out to modulator 120 via leadSDA of cable 116. To effect this, converter 1544 receives thetransmitter baud clock from lead TBD and a 9600 Hz line signal clockprovided by clock generator 1580 on lead LSC. The latter also extends tomodulator 120.

NDR clock 1548 receives the clocks on leads TBD and LSC. When all fourbits have been shifted out to modulator 120 from converter 1544, NDRclock 1548 provides an indication of this to the modulator via a pulseon lead NDR of cable 116.

Taps off of leads SDA and NDR and cable 1427 (in controller 1410) areextended to monitor register 1541 for examination by controller 30.

Clock generator 1580 is comprised of a phase-locked loop 1581, countdownchain 1584, double-buffered register 1587 and monitor register 1589.Phase-locked loop 1581 provides to countdown chain 1584 a 28.8 kHzsignal which, in normal data set operation, is either generatedinternally in response to the master clock signal on lead 26 or is phaselocked to a user-provided 4800 Hz signal on the TT lead of interfaceconnector 17. In loopback test modes, the output signal of phase lockedloop 1581 is phase locked to the 1600 Hz baud clock generated by decoder175 and extended to encoder 115 over lead 179. Three operating mode bitsfrom register 1587 determine which of these timing sources will be used.

The baud and bit clock frequencies generated by countdown chain 1584 inresponse to the phase-locked loop output are determined by two operatingparameter bits from register 1444, provided on cable 1446 within cable1467, and four operating parameter bits from register 1464, provided oncable 1466 within cable 1467. (The reason so many bits are used relatesto the fact that the countdown chain can be operated in numerous modeswhen encoder 115 is used in data sets which have multiplexingcapability.) The 4800 Hz bit clock, in addition to being providedinternally within the encoder over lead TBT, is also extended to the STlead of interface converter 17 over lead 117, as previously described.

Register 1589, in addition to the aforementioned two signals receivedfrom terminal interface 1310 over cable 1336, receives taps off the baudand bit clock leads for monitoring by controller 30.

Decoder

FIGS. 17-19, when arranged as shown in FIG. 20, depict decoder 175. Thearchitecture of decoder 175 is similar to that of encoder 115. Itincludes, in particular, a controller 1810 which controls six signalprocessing modules--terminal interface 1710, health monitor 1840,descrambler 1840, receiver interface 1910, differential decoder 1960,and delay module 1980.

Controller 1810 is very similar to controller 1410 of encoder 115. Itincludes a RAM/program counter (hereinafter referred to as RAM) 1826,which operates in response to control logic 1822. The latter convertsprogram instructions received from RAM 1826 into (a) select signals overdecoder select cable DS and (b) clock signals on decoder clock lead DC.The signals on these leads cause each of the signal processing modulesto operate on four-bit words provided from interface 1831 of controller1810 onto decoder outgoing data bus DOB and to return the processedwords to interface 1831 via decoder incoming data bus DIB.

Also similar to operations in controller 1410, program instructions areloaded into RAM 1826 from controller 30 via register 1819. RAMaddresses, both for initial program instruction loading and subsequentprogram counter loading, are provided via register 1817. (The latter isoperated in a double-buffered mode for program counter loading.)Configure, run, register read and register write bits are provided bycontroller 30 via register 1814.

Monitor register 1811 provides a different function from register 1411of controller 1410. Via one of the bits of register 1811, controller 30monitors the signal on lead 1915 of receiver interface 1910 used by thelatter to clock in serial data from circuit 170. Two other bits forregister 1811 are taken from control logic 1822 via cable 1824. One ofthose two bits indicates that controller 1810 has completed itsprocessing for the current baud interval. The other bit taken fromcontrol logic 1822 monitors the signal with which the control logicinitiates via a lead in cable 1823 each RAM instruction read. The fiveother bits of register 1811 monitor the RAM output on cable 1827.

Descrambler 1840 and differential decoder 1960 respectively provide theinverse functions of scrambler 1440 and differential encoder 1460 ofencoder 115. Descrambler 1840 includes a programmable descrambler 1841,the operating mode of which is specified by controller 30 via threeprocessing format bits from double-buffered register 1844 over cable1845. The operating mode of a programmable differential decoder 1961within differential decoder 1960 is controlled by two other processingformat bits of register 1844, provided over cable 1846.

The other two, operating mode, bits of register 1844 extend via cable1847 to a programmable delay 1981 within delay module 1980. In certainapplications, a user's terminal equipment may not be able to toleratethe erroneous "data" bits which are generated during receiver turn-off.In such applications, module 1980 provides a delay in the bit streamprovided to the user of either 15 or 21 bits (as determined fromcontroller 30). When the RR (receiver ready) lead is dropped at the endof a transmission, the above-mentioned erroneous bits are still withinmodule 1980 and thus are never extended to the user.

Health module 1835, which is principally comprised of double-bufferedhealth monitor register 1836, operates in the same manner, and providesthe same function, as health module 1340 of encoder 115.

Receiver interface 1910 is comprised of a clock selector 1914, countdownchain 1917, serial/parallel (S/P) converter 1921 and double-bufferedregister 1911. This module receives the signals extended to decoder 175by receiver processing and equalization circuit 170 via cable 171. Cable171, in particular, carries two signals; sliced data on lead SLD and thereceiver baud clock on lead RBD.

Countdown chain 1917, operative in response to the master clock signalon lead 26, generates numerous clock signals on its output leads 1918,with the countdown chain being reset in response to a reset signal fromreset circuit 1924 on lead 1925. The latter, in turn, generates thereset signal in response to the positive edge of the baud clock on leadRBD. (The reset signal also resets control logic 1822.) The signal oneach of leads 1918 has a different frequency from 1200 to 9600 Hz.Various ones of these signals are used in different ones of the datasets which decoder 175 is designed to operate in. Leads 1918 extend toclock selector 1914 via cable RCS. Two operating parameter bits fromregister 1911 on cable 1912 indicate to selector 1914 which of the clocksignals from the countdown chain is to be used as the bit clock for thisparticular data set. In the present example, as already noted, the bitrate is 4800 Hz.

The 4800 Hz signal is extended over lead 1915 to serial/parallel (S/P)converter 1921. This signal is used to clock in three bits per baudinterval from lead SLD. At the beginning each baud interval, the bitsshifted into converter 1921 during the previous baud interval are loadedin response to a clock pulse on lead DC into a register within S/Pconverter 1921 from which they are read by controller 1810 via bus DIB.

A cable 1916 carries a number of signals from receiver interface 1910 toterminal interface 1710. These include the signals on leads RBD and SLDand cable RCS. Also included in cable 1916 is a cable TIC, which carriessignals from register 1911.

Terminal interface 1710 receives over bus DOB from controller 1810fully-decoded data bits formatted in three-bit words, which are loadedinto P/S converter 1729 in response to a clock signal on lead DC.Converter 1729 receives baud and bit clocks from cable RCS via clockselector 1726 and leads 1727 and 1728, respectively. The particular onesof the cable RCS signals to be applied to leads 1727 and 1728 areindicated to selector 1726 by controller 30 via operating parameter bitsin double-buffered register 1723.

The serial output bits of parallel/serial converter 1729 are provided onlead 1730. From there, they extend to RD clamp 1714 which, depending onan operating mode bit in double-buffered register 1711 on lead 1712,either passes the data bits through to decoder output lead 176 or clampsthat lead high. Another bit in register 1711, provided on lead 1713,controls RR (receiver ready) latch 1717, the output of which is decoderoutput lead 182.

The baud and bit clocks on leads 1727 and 1728, respectively, areprovided on decoder output leads 179 and 174, respectively. These twosignals, as well as the data bit stream itself, are also extended tomonitor register 1721 for inspection by controller 30. The bit stream onlead 1730 and the bit clock on lead 1728 also extend to pseudo-randomword (PRW) comparator and error counter (hereinafter referred to as PRWcomparator) 1738, word trap 1734 and data buffer 1756.

More particularly, PRW comparator 1738 operates during various tests to(a) compare the received bits to a known pseudo-random word transmittedrepetitively from the far end data set or (b) determine in a so-calleddata set self test whether the data stream is comprised of all bits inthe set state. The number of transmission errors detected is countedwithin comparator 1738 and is provided to controller 30 viadouble-buffered monitor register 1741. Three bits from register 1911 (inreceiver interface 1910) extend to PRW comparator 1738 via cable TIC--aportion of cable 1916. Two of these bits determine whether the receiveddata stream will be examined for a 15-bit pseudo-random word, a 511-bitpseudo-random word or the stream of bits all in the set state. Anotherbit is used to clear the error counter within the element 1738.

Word trap 1734 generates the above-described word trap interrupt on lead177 when a particular word loaded into register 1731 by controller 30 isdetected in the bit stream on lead 1730. The word trap indication isheld in a latch within the word trap, that latch being reset upon thewriting of a new word into register 1731. Register 1731 isillustratively comprised of two eight-bit register so that a word of upto sixteen bits can be matched to. The actual number of bits fromregister 1731 to be used in performing the matching is indicated to wordtrap 1734 by controller 30 via three bits of register 1746 on cable1747.

Counter 1749 and data buffer 1756 provide controller 30 with the abilityto examine in parallel eight bits of the serial bit stream, with thebits being framed in response to the occurrence of a match signaled byword trap 1734. In operation, the lead 1730 bit stream is clockedserially into buffer 1756. The occurrence of a match, as signaled by apulse on lead 1735, resets counter 1749. After eight bit clock pulsesfrom lead 1728, counter 1749 pulses data register 1752 over lead 1751,causing it to load the eight bits then in buffer 1756 into register1752. A bit from register 1746 on lead 1748, when set, inhibits counter1749 from resetting in response to a word trap match. This prevents anerroneous resetting of the counter should a stream of bits in thereceived data happen to match the word in register 1731.

Four bits of monitor register 1743 provide the ID word for the decoder.Two other bits carry the signals on leads RBD and SLD. One other bitextends from word trap 1734 on lead 177. Another bit of register 1743,provided on lead 1753 by control circuitry associated with register1752, is set when register 1752 is loaded with new data and cleared whenthat register is read.

Modulator

Modulator 120, shown in FIG. 21, is principally comprised of amicrostore/sequencer (hereinafter microstore) 2135, arithmetic unit 2141and a number of registers.

Once per baud interval, a four-bit data word is shifted into an inputregister 2111 from encoder 115 over lead SDA of cable 116. As previouslynoted, each data word represents a carrier angle for the modulated datasignal to be transmitted. The bits of the data word are clocked intoregister 2111 in response to the 9600 Hz line signal clock provided byencoder 115 on lead LSC of cable 116. The data is transferred inparallel form into a hold buffer 2113 in response to the signal on leadNDR. In normal operation, the output of buffer 2113 extends via selector2122 and cable 2123 to arithmetic unit 2141. The latter provides theinput to D/A converter 125 over cable 121.

Arithmetic unit 2141 contains circuitry such as adders, multipliers,multiplexers and random access and read-only memories. At any one time,the sequence of arithmetic operations performed by this circuitry ingenerating the modulated data signal is controlled by an appropriate oneof four programs stored in microstore 2135 and extended to arithmeticunit 2141 over cable 2136. Three of the four programs define the orderof arithmetic operations to be performed in providing respective ones ofthe three above-mentioned modulation formats. The fourth program definesthe order of arithmetic operations needed to generate the tone sequencesused to perform various tests. Microstore 2135 operates in response tothe master clock signal on lead 26 and to the signals on leads LSC andNDR.

A 16-bit operating parameter word specifying the primary channel carrierfrequency is provided to arithmetic unit 2141 by controller 30 viaregister 2146, which is illustratively comprised of two eight-bitregisters. Controller 30 is also able to read these registers to verifythat the correct carrier frequency value remains stored therein.

Register 2125 provides several functions. An operating mode bittherefrom extends to selector 2122 over lead 2126 to indicate whetherthe selector should take as its input signal the user-provided datawords from hold buffer 2113 or jam data words provided from controller30 via register 2116 during, for example, the generation of test tones.Another operating mode bit of register 2125 extends to arithmetic unit2141 over lead 2127 and indicates whether the modulator is to be on oroff.

Another four bits from register 2125 are extended to microstore 2135over cable 2128. Three of them are processing format bits which identifywhich of the four programs stored in the microstore are to be used and,in the case of the test program, they also identify which of these readonly memories within the arithmetic unit (which include baseband shapinginformation) are to be used. The fourth bit indicates whether thecurrent line signal value or the current carrier angle is to be loadedinto monitor register 2143 from arithmetic unit 2141.

Monitor register 2131 provides controller 30 with a way of monitoringthe signals on leads 26, SDA, NDR and LSC. Register 2119 holds themodulator ID word.

Receiver Processing and Equalization Circuit

Receiver processing and equalization circuit 170 is comprised of aplurality of LSI circuits, one of which is receiver controller 170a andanother of which is receiver processor 170b. A third element of circuit170, equalizer 170c, is itself illustratively comprised of two LSIcircuits.

The basic data signal flow through circuit 170 is as follows: TheHilbert transform signals generated by A/D converter are received oneafter the other on cable 166 along with a signal indicating that theanalog-to-digital conversion is complete. Cable 166 extends to receiverprocessor 170b which, upon detecting line signal energy, provides theenergy detect interrupt signal on lead 173. Receiver processor 170bthereafter operates in conjunction with equalizer 170c with which itcommunicates over two-way cable 2248, to equalize and demodulate thereceive line signal and form data decisions therefrom. The datadecisions are provided via receiver controller 170a to decoder 175 overlead SLD. Receiver processor 170b also provides to AGC 155 over cable172 the above-mentioned digital word specifying the AGC gain and clocksignals for the AGC.

Both receiver processor 170b and equalizer 170c can be realized in anyof numerous ways which will be apparent to those skilled in the art.Moreover, neither receiver processor 170b nor equalizer 170ccommunicates directly with controller 30. Rather, all informationtransfer between controller 30,on the one hand, and receiver processor170b and equalizer 170c, on the other hand, is effected via registers inreceiver controller 170a. In view of those considerations, thedescription herein of the receive processor and equalizer is limited totheir interaction with the receiver controller.

Receiver controller 170a is comprised of a timing circuit 2246, registercontrol circuit 2236 and a plurality of registers which controller 30either reads from or writes into over bus PD. Registers 2222, 2231 and2241 are unbuffered. Each of the other registers is double buffered.(The concept of double buffering is described hereinabove in conjunctionwith encoder 115.)

Timing circuit 2246 receives as its inputs the baud-frequency squarewave signal provided by phase splitter/timing recovery circuit 160 overlead 162. It also receives the master clock signal over lead 26. (Themaster clock signal also extends to receiver processor 170b. Equalizer170c receives a different master clock signal (not shown) than the otherLSI circuits.) The operation of timing circuit 2246 is controlled by twooperating parameter bits from register 2241, which specify the bit ratefor data set 10. Another, operating mode, bit from register 2241determines whether the timing recovery circuitry within the circuit 2246is to operate or be inhibited, e.g., during receiver start-up.

The outputs of timing circuit 2246 include a receiver baud clock on leadRBD. This signal extends to receiver processor 170b; equalizer 170c;decoder 175 via cable 171; monitor register 2222; and register controlcircuit 2236. The baud clock is monitored by controller 30 via a bit inregister 2222.

Timing circuit 2246 also generates a 307 kHz clock and a clock having afrequency of twice the baud frequency, both of which are extended to A/Dconverter 165 over cable 167. The other outputs of timing circuit 2226are discussed hereinbelow.

The registers into which controller 30 writes includes registers 2212,2217, 2227, 2231 and 2241 (the latter having already been discussed).

During data set initialization, controller 30 uses registers 2212 and2217 to load into a RAM within receiver processor 170b operatingparameters relating to such items as carrier frequency, ideal decisionpoints, etc. In particular, the information itself is loaded intoregister 2217 and the associated RAM address is loaded into register2212. The bits in registers 2212 and 2217 are serially shifted toreceiver processor 170b via lead 2213, with the bits from register 2217passing through register 2212 via lead 2218. The shifting of these bitsis controlled by a clock signal provided by timing circuit 2246 on alead RC1. This process continues until the receiver processor RAM hasbeen fully loaded. Control bits in each of register 2212 and 2217indicate to receiver processor 170b that the information in theregisters is, in fact, RAM information.

While receiver processing is ongoing, the control bits in register 2212and 2217 indicate that the information in the registers is not RAMinformation but, rather, control information for the receiver processor.This control information includes, for example, two operating parameterbits in register 2217 indicating the adaptation step size to be used inupdating equalizer coefficients. Another, operating mode, bit indicateswhether the equalizer is to operate in normal or retrain modes. Threeoperating parameter bits determine the step size to be used in updatingthe AGC gain. Two operating parameter bits are comprised of idealreference data from register 2227, as described below. The controlinformation in register 2212 includes two bits indicating whether theequalizer should be operated in normal or start-up modes. Another twobits comprise a mode control signal, defining whether the receiverprocessor should operate in a normal mode, test mode, start-up mode(with decision-directed equalizer coefficient updating) or idealreference mode (in which equalizer coefficient updating is performed inresponse to ideal reference data). Another operating mode bit determineswhether the equalizer should be bypassed altogether and another defineswhich of two algorithms are to be used in updating the AGC gain. Theshifting of the information from registers 2212 and 2217 into thereceiver processor during received signal processing is effected onceper baud interval.

Register 2227 receives ideal reference data for four symbols at a time(two bits per symbol) from controller 30. When circuit 170 is in anideal reference start-up mode, control circuitry (not shown) operatesregister 2227 to cause the ideal reference data stored therein to shifttwo bits over. As each successive two bits reach the end of register2227, they are loaded over cable 2228 into two bit positions of register2217. The ideal reference bits thus loaded into register 2217 arethereafter shifted into receiver processor 1706 as previously described.A signal is provided from register 2227 on lead 2229 indicating whenregister 2227 is ready to receive new ideal reference data. This signalis provided to controller 30 via a bit of monitor register 2222 (whichalso provides the circuit 170 ID word).

Register 2231 provides three operating mode bits to equalizer 170c overcable 2233. Two of these bits define a control signal for the equalizercoefficients indicating, in particular, whether the equalizer shouldupdate the coefficients normally; inhibit coefficient updating; set thecenter tap equal to unity and all other coefficients to zero; or set allthe coefficients equal to zero. The third bit enables and equalizer taprotation control circuitry. Another operating mode bit from register2231 extends to timing circuit 2246 over lead 2234 and, when set,indicates that the timing recovery circuitry therein is to continue torun even if carrier has apparently been lost. This capability is used tobridge apparent carrier losses.

Two other bits in register 2231 comprise register write and registerread bits, respectively, for the double-buffered registers of receivercontroller 170a. These bits extend to register control circuit 2236 overcable 2232. Upon receiving a baud clock pulse over lead RBD, circuit2236 generates a transfer pulse on lead 2237 if the register write bitis set. Lead 2237 extends to each of the double-buffered registers intowhich controller 30 writes, and the transfer pulse thereon effects atransfer of information from the outside to the inside portion of eachof these registers. Circuit 2236 similarly extends a transfer pulse toeach double-buffered monitor register over lead 2238 and monitorregister cable MRC.

The registers of receiver controller 170a not yet described are allmonitor registers. In particular, the Hilbert transform components fromcable 166, in addition to being applied to receiver processor 170b, areread into monitor registers 2202 and 2207 for inspection by controller30. The remaining monitor registers receive their inputs from receiverprocessor 170b. Register 2201 holds the AGC gain value. Registers 2206and 2211 hold the so-called in-phase (I) and quadrature-phase (Q)unsliced demodulated line signal values. Depending on whether theabove-mentioned receiver processor mode control bits in register 2212indicate normal or test mode, (a) register 2216 contains the eight bitsstored in the receiver processor RAM at the location specified bycontroller 30 in register 2212 or it contains a word representing theline signal power and (b) register 2221 contains the present carrierphase angle or it contains the value (sin² θ+cos² θ), where θ is thatangle. Three bits of register 2226 hold sliced data decisisons and onebit indicates that carrier has been detected.

The bits to be loaded into these monitors registers from receiverprocessor 170b are provided by the latter serially on a lead withinreceiver processor data cable RPD, accompanied by a clock signal onanother lead within that cable. Register control circuit 2236,responsive to the baud clock on lead RBD and a clock from timing circuit2246 on lead RC2, pulses each of these monitor registers over arespective lead of a register control cable RCC--which is containedwithin cable MRC. As each register is pulsed, it is enabled to take inthe next eight bits appearing on the data lead within cable RPD.

Register 2226 also receives a bit clock from timing circuit 2246 overlead BC. This clock is used to serially shift out to decoder 175 overlead SLD the three bit sliced data decision stored in the register.

SECONDARY CHANNEL CIRCUITRY

As previously indicated, the secondary channel circuitry--also referredto as the Data set Diagnostic Unit (DDU)--is controlled by a controller50. Controller 50 is structured similarly to controller 30. It includesa microprocessor 510, ROM 515, RAM 520, timer circuitry 525, interruptcontroller 530 and chip select decoder 535. Controller 50 communicateswith its peripherals and the rest of the DDU--secondary signalprocessing circuitry 40, diagnostic channel circuitry 70 and secondaryI/O circuitry 90--via secondary address bus SA, control bus SC, data busSD and chip select cable SCS. The latter is comprised of the outputleads 536 of decoder 535.

Secondary signal processing circuitry 40, as previously noted, receivesthe output of preamplifier 16. Within circuitry 40, the signal isreceived by secondary channel filter 405 which removes the primarychannel receive signal and passes the FSK secondary channel receivesignal to receiver 410. The latter provides an output pulse on lead 411in response to each zero crossing of the FSK signal. These zero crossingindications are extended to microprocessor 510 via interrupt controller530 and interrupt lead 531. The microprocessor through an algorithmwhich includes measuring of the time intervals between successive zerocrossing interrupts. It does this with the aid of timer 525b, from whicha count is read on bus SD. (Also operating in a divide-by-N mode istimer 525c, the interrupts of which define a 110 baud clock for thesecondary channel.)

Secondary channel transmitter 415 receives from controller 50information to be transmitted over the secondary channel. Transmitter415 is illustratively an FSK transmitter which implements the inventionsdisclosed in U.S. Pat. Nos. 4,170,764 issued Oct. 9, 1979, to J. Salz etal and 3,801,807 issued Apr. 2, 1974 to J. Condon. The output oftransmitter 415 passes to adder 15 via lead 416. Signals from which thefrequencies of the two FSK tones are derived are provided to transmitter415 from timer 525a via one of leads 526.

Secondary I/O circuit 90 includes a pair of latches 91, one-shot 93 andLED 94. The outputs of latches 91 extend to transmitter 415 over cable92. One of these latch outputs turn transmitter 415 on and off. Theother latch output determines which of two predetermined amplitudes thetone currently being transmitted by transmitter 415 is to have; asdescribed in the Salz et al patent, the higher frequency tone has asmaller amplitude than the lower frequency tone. One-shot 93 is pulsedperiodically (e.g., at 10 Hz) by controller 50 whenever a message isbeing transmitted or received on the secondary (diagnostic) channel.This causes a blinking of diagnostic channel indicator 94 on front panel701.

Tests and commands can be initiated by the user not only from the frontpanel, as described below, but via diagnostic control device (DCD) 75which is physically distinct from the data set. The DCD communicateswith controller 50 asynchronously via diagnostic channel circuitry 70.The latter includes a DCD interface 71 and universal asynchronousreceiver and transmitter (UART) 72 which formats and de-formats theasynchronous data. A clock for UART 72 is provided from timer 525f.Timers 525d and 525e are used for general purpose interrupt timing.

Communication between controllers 30 and 50 via bus interface 60 arecarried out a character at a time. Bus interface 60 is illustratively acommercially available circuit known as a parallel peripheral interface.When controller 50 writes a character into the interface, it sets a flagwithin the interface. This flag is read over lead 61 and one of buffers84 by a function which is called within controller 30 between each tasktable task. If the flag has been set, the character stored by controller50 is read by controller 30 and stored in DDU buffer 1165. The readingof the character automatically resets the flag. Controller 50periodically monitors the flag and if it has more characters to pass tocontroller 30, it loads it into interface 60 once the flag has beenreset. DDU handler task 921, when executed, reads the contents of buffer1165 and, if it finds a complete message, acts upon it, as described infurther detail below.

Information is passed from controller 30 to controller 50 in a similarfashion.

The secondary channel circuitry, or DDU, performs three basicfunctions--DDU background diagnostics, network health monitoring andmessage routing. The DDU background diagnostics include various checksof the circuitry within the DDU to ascertain that it is operatingproperly. These checks are similar to ones performed on the primary sideof the data set. Network health monitoring includes the polling of thedownstream network (comprised, in this example, of a single data set) toobtain information as to how it is functioning--its so-called "health."It also includes the receipt of health information from the primarychannel circuitry. All of this health information is held in RAM 520 andis provided to the primary channel circuitry and DCD 75 for display tothe user.

The message routing function of the DDU provides for the orderly flow ofmessages among the primary channel circuitry (via interface 60), thenetwork (via circuitry 40) and the DCD (via circuitry 70). The messagesinclude such information as data set health, as mentioned above, thesetting up and aborting of tests requested from front panel 701 or DCD75 and the reporting of test results back to the front panel or DCD.

COMMANDS AND TESTS

This portion of the detailed description sets forth an example of howthe data set provides the user with the ability, via front panel 701, to(a) change options under which the data set operates and (b) request therunning of a test between the two data sets. This descriptionillustrates the operational interrelationship of various tasks and alsoillustrates controller 30/controller 50 communication.

Suppose the user wishes to change a data set option, such as changingits operation from continuous carrier to switched carrier. This optionchange is effected by issuing a "change option" command to the data set,a procedure which is initiated by selecting the CMD (command) positionof TEST/CMD rocker switch 85 on the front panel. The positions of all ofswitches 85 are read in each pass through task table 1001 by one ofcommunications control tasks 911 referred to as the scan task. Upondetermining that this is a new position for the TEST/CMD switch, thescan task initializes a menu address pointer 1151 within RAM 320 to theaddress of the first line entry of a test/command menu. The latter is atable 1201, shown in FIG. 12, stored within data files 964 of ROM 315.

The scan task examines a particular bit position within the multi-bitflag associated with the first entry of table 1201. This bit indicateswhether the entry relates to a test or command. The first entryillustratively relates to a test. Upon determining this, the scan taskadvances the menu address pointer to the address of the next line entry,and so forth, until a command is encountered. Other bits within the flagare then examined to determine the data set configuration for which thecommand is valid. For example, certain commands, including the changeoptions command, are valid only if the data set is in a so-calledmaintenance mode. (Data set 10 is presumed in this example to havealready been placed in the maintenance mode via execution of amaintenance mode command (mnemonic MTNC). Other commands are valid for acontrol data set but not a tributary, etc. A data set status word 1161in RAM 320 indicates the current configuration of data set 10 and thisword is used to determine whether the command under consideration isvalid.

Assuming that the command is valid, the scan task reads a mnemonic forthe command--illustratively MDCK--(modem check)--from the mnemoniccolumn of table 1201 and loads it into a display buffer 1155 within RAM320. The scan task then calls a function which controls display 87. Thelatter, in turn, reads the display buffer contents and presents themnemonic on display 87. Since the user does not wish to execute themodem check command, he or she will now push and hold the BWD/FWD(backward/forward) momentary contact rocker switch 85 to the FWDposition. As long as the BWD/FWD switch is depressed, the scan taskperiodically scrolls through the command menu by advancing menu addresspointer 1151 approximately once per second to the line entry of the nextvalid command and causes its mnemonic to be displayed, and so forth.(Reverse scrolling is achieved by depressing the BWD/FWD switch to theBWD side.)

When the mnemonic for the change options command--CHOP--appears, theuser releases the BWD/FWD switch and pushes the EXECUTE switch. The scantask now examines the flag associated with this line entry to determinewhether the +/- switch must be operated before the command can beexecuted. In this case, the +/- switch is used to identify the option tobe changed. Accordingly, the scan task now causes CH** to be displayedby writing that character string into display buffer 1155. The ** tellsthe user that the +/- switch is to be depressed. Associated with eachoption is a two-character alphanumeric, e.g., A1, B3, C4. As the +/- isheld depressed (to one side or the other) the scan task causes to besequentially displayed (in forward or reverse order) the optionalphanumerics for this type of data set, which are read from a table inROM 315. If the option is currently installed, as determined from atable in RAM 320, it also displays a check mark, e.g., √B3.

If the user now pushes the EXECUTE button again, the displayed option,if not installed, will be installed and vice versa. In particular, thescan task sets a flag in RAM 320 indicating that a command waits to beexecuted and also indicating the source of the command (front panel orDDU). This flag is read in the background by one of tests and commandstasks 951 referred to as the test manager.

The test manager looks at the current value of menu address pointer 1151and finds in the front panel function column (since the command issuedfrom there), the address within tests and command filed 952 of thefunction which will effect the option change. The test manager transferscontrol to that function and the latter changes the option. As anotherexample, suppose that the user wishes to run a transmit loss test whichinvolves a measurement by the far-end modem of the receive level of atone--illustratively at 1004 Hz--transmitted from data set 10 over theprimary channel of transmit line 11. Tests are initiated by depressingthe TEST side of the TEST/CMD switch, Now, as the BWD/FWD switch isdepressed, only mnemonics for tests are displayed. The BWD/FWD switch isreleased by the user when the mnemonic for the test of interest--in thiscase, TRAN--appears on the display. (As with the change options command,the data set must have been already placed in the maintenance mode forthis test.) Pushing the EXECUTE switch causes TR** to appear on display87, indicating that the +/- switch is to be depressed until the twodigit address of the far end data set that is to make the transmit lossmeasurement appears on the display. (In this example, of course, thereis only one far-end data set.)

As before, the scan task, in response to a second pushing of the EXECUTEswitch, sets a flag for the test manager. The latter responds by lookingup the address of the appropriate function in table 1201 and transferscontrol thereto.

Before proceeding with a discussion of the set-up of the transmit losstest, it is useful to describe briefly the protocol which governscommunication between the controllers 30 and 50. Controller 30 is alwaysin a responsive mode with respect to controller 50. That is, the latteralways initiates the communication. Controller 50 does this byperiodically transmitting (via interface 60) an inquiry message tocontroller 30 which is stored in DDU buffer 1165.

DDU handler task 921, when executed, reads the inquiry and, if it hasnothing else to respond with, responds with a message indicating thehealth of the primary channel circuitry, as read from health word 1101.If there are no faults to report, this fact is reported to controller50. If there are faults, these are reported. This health information isstored by controller 50 in RAM 520 along with health reports receivedfrom the far end data set.

DDU handler task 921 also monitors one of DDU flags 1167 which is setperiodically by one of communication control tasks 911--referred to asthe status reporting task. This flag indicates that the status reportingtask wishes to receive the health information compiled by controller 50.If the DDU handler tasks finds that this flag has been set, it respondsto the inquiry from controller 50 not with an indication of primarychannel circuitry health, but with a word which asks if controller 50 isfree to accept a message. Controller 50 responds negatively if, forexample, a test is in progress and it is waiting for results to bereported back from the far end data set. If, however, controller 50responds positively, the DDU handler task transmits the messagerequested by the status reporting task, viz., a request for a networkhealth report.

The requested information is thereupon written into interface 60 bycontroller 50 and is read by the DDU handler. The latter, in turn,stores the network health information in RAM 320 which it is read by thestatus reporting task. If a fault has been reported, the statusreporting task switches status indicators 82 to red/on, green/off andloads into display buffer 1155 appropriate mnemonics for the faultsdetected.

Like the status reporting task, the test manager raises one of DDU flags1167 when it wants to run a test which involves the DDU. In the case ofthe transmission loss test currently under discussion, use of the DDU isrequired since the far end data set must be prepared to receive thetone, measure the received signal level and report back the results.

Once the DDU handler receives an OK from controller 50 to transmit amessage, it puts into interface 60 a message for the far end data setwhich instructs that data set to prepare for a test by entering aso-called test mode. Controller 50 upon examining the message,determines that it is not directed to it, but rather, is to betransmitted out over the secondary channel. It accordingly transmits themessage.

When a confirmation is received from the far end data set that it isprepared to run a test, controller 50 passes this information tocontroller 30 which thereupon instructs the far end data set to preparefor the transmit loss test. Upon receiving a confirmation that thisinstruction was received, controller 30 causes modulator 120 to transmitthe 1004 Hz tone over the primary channel at 0 dbm for 5 seconds.Controller 50 continually polls the far end data set for test results.Upon receipt of the test results--a measurement of received signal levelin dbm--controller 50 passes them along to the DDU handler, which, inturn, calls a function which causes the results to be presented ondisplay 87. Controller 30 then instructs the far end data set toterminate the transmit loss test and upon receiving confirmation ofsame, instructs it to leave the test mode.

Although a specific embodiment of an invention is shown and describedherein, this merely illustrates the principles of the invention. Thoseskilled in the art will be able to devise numerous arrangementsembodying these principles without departing from their spirit andscope.

We claim:
 1. A data set for processing data applied to said data set togenerate transmit telephone voiceband data signals representing saiddata, said data set characterized bysignal processing means whichincludes a plurality of addressable registers, a bus common to saidregisters, and controller means for addressing said registers forwriting into each register via said bus at least a first associatedinformation signal, the values of the information signals in saidregisters specifying the manner in which said data are to be processed,said signal processing means further including circuit means distinctfrom said controller means for processing said data in accordance withsaid information signal values to generate said transmit telephonevoiceband data signals, and means for applying said transmit telephonevoiceband data signals to a telephone line.
 2. A data set for processingreceived telephone voiceband data signals applied to said data set torecover far-end data characterized bysignal processing means whichincludes a plurality of addressable registers, a bus common to saidregisters, and controller means for addressing said registers and forwriting into each register via said bus at least a first associatedinformation signal, the values of the information signals in saidregisters specifying the manner in which said received telephonevoiceband data signals are to be processed, said signal processing meansfurther including circuit means distinct from said controller means forprocessing said received telephone voiceband data signals in accordancewith said information signal values to recover said far-end data.
 3. Adata set for processing data applied to said data set to generatetransmit telephone voiceband data signals representing said data, andfor processing received telephone voiceband data signals applied to saiddata set to recover far-end data characterized bysignal processing meanswhich includes a first plurality of addressable registers and a secondplurality of addressable registers a bus common to said first and secondpluralities of addressable registers, and controller means foraddressing said registers and for writing into each register via saidbus at least a first associated information signal, the values of theinformation signals in said first plurality registers specifying themanner in which said data are to be processed and the values of theinformation signals in said second plurality registers specifying themanner in which said received telephone voiceband data signals are to beprocessed, said signal processing means further including circuit meansdistinct from said controller means for processing said data inaccordance with the information signal values in said first pluralityregisters to generate said transmit telephone voiceband data signals andfor processing said received telephone voiceband data signals inaccordance with the information signal values in said second pluralityregisters to recover said far-end data, and means for applying saidtransmit telephone voiceband data signals to a telephone line.
 4. Theinvention of claims 1 or 2 wherein said controller means includesbackground means operative for repetitively monitoring predeterminedsignals within said data set and for performing predetermined actions asa function of the values of said predetermined signals.
 5. The inventionof claim 4 wherein said signal processing means further includes meansfor generating an interrupt signal in response to at least a firstpredetermined signal event within said signal processing means andwherein said controller means further includes interrupt service meansfor suspending the operation of said background means in response to thegeneration of said interrupt signal and for writing predeterminedinformation signals into the associated ones of said registers, thevalues of said predetermined information signals being associated withsaid signal event.
 6. The invention of claim 5 wherein said backgroundmeans includes means for identifying said predetermined informationsignal values.
 7. The invention of claim 4 wherein said background meansincludes means (901) for checking the integrity of the circuitry of saiddata set and for providing an indication if a fault in said circuitry isdetected.
 8. The invention of claims 1, 2 or 3 wherein at least ones ofsaid information signals specify operating modes for said signalprocessing means.
 9. The invention of claims 1, 2 or 3 wherein at leastones of said information signals specify operating parameter values forsaid signal processing means.
 10. The invention of claims 1, 2 or 3wherein at least ones of said information signals specify signalprocessing formats for said signal processing means.
 11. The inventionof claims 1, 2 or 3 wherein said circuit means includesmeans forperforming at least a portion of said processing in response to a set ofprogram instructions stored within said circuit means, and means adaptedto receive said program instructions from said controller means prior toinitiation of said processing.
 12. A data set comprisingsignalprocessing means including means for encoding user-provided data inaccordance with at least a specified one of a plurality of predeterminedencoding formats, and means for applying to a voiceband telephonechannel a transmit data signal generated in response to the encoded datain accordance with a specified one of a plurality of predeterminedmodulation formats useable over voiceband telephone channels, saidsignal processing means further including a plurality of registers, abus common to said registers, and a stored-program-controlled processordistinct from said signal processing means and including means forwriting information signals into ones of said registers via said bus,ones of said information signals specifying to said signal processingmeans said encoding and modulation formats.
 13. The invention of claim12 whereinsaid data set further comprises a request-to-send lead, thesignal on which has a first value if the user desires to provide data tosaid signal processing means and a second value otherwise, and means forgenerating an interrupt signal when the signal on said request-to-sendlead switches to said first value, said signal processing means iscontrollable in response to other predetermined information signalswritten into others of said registers to generate a predeterminedstart-up signal and to apply said start-up signal to said channel aheadof said transmit data signal, said processor further includes backgroundmeans operative for detecting faults in at least predetermined portionsof the circuitry comprising said data set and means for performingpredetermined actions when such faults are detected, and said processorfurther includes interrupt service means operative in response to saidinterrupt signal for suspending the operation of said background meansand for controlling said signal processing means to generate saidstart-up signal by writing said other predetermined information signalsinto said others of said registers.
 14. The invention of claims 12 or 13wherein ones of said predetermined encoding formats are scramblingformats and others of said predetermined encoding formats aredifferential encoding formats.
 15. The invention of claim 14 wherein atleast one of said predetermined modulation formats is aphase-shift-keying format and at least another is aquardature-amplitude-modulation format.
 16. The invention of claim 15wherein others of the information signals written into said ones of saidregisters specify bit and baud rates.
 17. A data set comprisingsaidprocessing means including means for demodulating a passband data signalreceived by said data set from a voiceband telephone channel, saidpassband data signal representing encoded data, and for decoding thedemodulated signal in accordance with at least a specified one of aplurality of predetermined decoding formats, said signal processingmeans further including a plurality of registers, a bus common to saidregisters, and a stored-program-controlled processor distinct from saidsignal processing means and including means for writing informationsignals into ones of said registers via said bus, ones of saidinformation signals specifying to said signal processing means saiddecoding formats.
 18. The invention of claim 17 whereinsaid data setfurther comprises means for generating an interrupt signal in responseto reception of said data signal, said signal processing means iscontrollable in response to other predetermined information signalswritten into others of said registers to process an initial portion ofsaid data signal to initiate the operation of said demodulating anddecoding means, said processor further includes background meansoperative for detecting faults in at least predetermined portions of thecircuitry comprising said data set and means for performingpredetermined actions when such faults are detected, and said processorfurther includes interrupt service means operative in response to saidinterrupt signal for suspending the operation of said background meansand for controlling said signal processing means to process said initialportion by writing said other predetermined information signals intosaid other of said registers.
 19. The invention of claims 12, 13, 17 or18 wherein others of the information signals written into said ones ofsaid registers specify bit and baud rates.
 20. The invention of claims17 or 18 wherein ones of said predetermined decoding formats aredescrambling formats and others of said predetermined decoding formatsare differential decoding formats.
 21. The invention of claim 20 whereinothers of the information signals written into said ones of saidregisters specify bit and baud rates.
 22. A data set whichincludestransmitter means operative for generating in response tonear-end data a data signal representing said near-end data and adaptedfor transmission over a voiceband telephone channel, said transmittermeans including a plurality of individual circuits each of which has atleast two selectable operating modes, and further including means forappying said data signal to a voiceband telephone channel,initialization means operative for placing at least ones of saidcircuits in respective initial ones of said operating modes, backgroundmeans operative subsequent to the operation of said initializationmeans, said background means including means for monitoringpredetermined signals within said data set and operative in response toa determination from the values of ones of the monitored signals that afault exists in said data set for providing a fault indication, meansfor generating an interrupt signal in response to an indication from asource external to said data set that operation of said transmittermeans is desired, and interrupt service means operative in response tosaid interrupt signal for suspending the operation of said backgroundmeans and for controlling the operating modes of at least ones of saidtransmitter circuits in such a way as to effect a start-up operation ofsaid transmitter means.
 23. A data set which includesreceiver meansoperative for recovering far-end data from a data signal representingsaid far-end data and received from a voiceband telephone channel, saidreceiver means including a plurality of individual circuits each ofwhich has at least two selectable operating modes, initialization meansoperative for placing at least ones of said circuits in respectiveinitial ones of said operating modes, background means operativesubsequent to the operation of said initialization means, saidbackground means including means for monitoring predetermined signalswithin said data set and operative in response to a determination fromthe values of ones of the monitored signals that a fault exists in saiddata set for providing a fault indication, means for generating aninterrupt signal in response to the initial reception of said datasignal, and interrupt service means operative in response to saidinterrupt signal for suspending the operation of said background meansand for controlling the operating modes of at least ones of saidreceiver circuits in such a way as to effect start-up operation of saidreceiver means.
 24. A data set which includestransmitter means operativefor generating in response to near-end data a data signal representingsaid near-end data, said transmitter means including means for applyingsaid data signal to a voiceband telephone channel, receiver meansoperative for recovering far-end data from a data signal representingsaid far-end data received from a voiceband telephone channel, saidtransmitter means and said receiver means each including a plurality ofindividual circuits each of which has at least two selectable operatingmodes, initialization means operative for placing at least ones of saidcircuits in respective initial ones of said operating modes, backgroundmeans operative subsequent to the operation of said initializationmeans, said background means including means for monitoringpredetermined signals within said data set and operative in response toa determination from the values of ones of the monitored signals that afault exists in said data set for providing a fault indication, meansfor generating a first interrupt signal in response to an indicationfrom a source external to said data set that operation of saidtransmitter means is desired, means for generating a second interruptsignal in response to the initial reception of said received datasignal, and interrupt service means operative in response to said firstand second interrupt signals for suspending the operation of saidbackground means and for controlling the operating modes of ones of saidcircuits in such a way as to effect start-up operations of saidtransmitter means and said receiver means, respectively.
 25. Theinvention of claims 22, 23 or 24, wherein said background means furtherincludes means for monitoring user-controlled signals the values ofwhich are indicative of respective actions to be executed by said dataset and means responsive to each said value for initiating the executionof the respective action.
 26. The invention of claim 25 wherein at leastone of said user-controlled signals is indicative of a test to beperformed by said data set.
 27. The invention of claim 25 wherein atleast one of said user-controlled signals is indicative of a change tobe made in the operating mode of at least one of said circuits.
 28. Theinvention of claims 23 or 24 wherein said background means furtherincludes means for monitoring at least a fire signals within said dataset indicative of predetermined parameter of said received data signaland, if said parameter is not within predetermined limits, forinitiating remedial action to bring said parameter within said limits.29. The invention of claim 28 wherein said receiver means is adapted tooperate utilizing a plurality of alternative signal processing formatsand wherein said remedial action includes causing said receiver means tooperate with at least one changed operating mode or signal processingformat.
 30. The invention of claim 24 wherein said interrupt servicemeans is operative for effecting at least one of said start-upoperations in at least two alternate ways depending on the currentoperating mode of at least one of said circuits and wherein saidbackground means further includes means for predetermining for saidinterrupt service means, as a function of said current operating mode,which of said alternate start-up operations is to be effected.
 31. Theinvention of claims 22, 23 or 24 wherein the operating modes of at leastone of said circuits are "on" and "off".
 32. The invention of claims 22,23 or 24 wherein at least one of said circuits distributes timingsignals to others of said circuits and has as at least ones of itsoperating modes the generation of said timing signals in response torespective timing sources.
 33. The invention of claims 22 or 24 whereinat least one of said circuits obtains said near-end data and has as onesof its operating modes the obtaining of said near-end data fromrespective data sources.
 34. The invention of claim 33 wherein one ofsaid data sources provides as said near-end data at least a firstpredetermined start-up data signal.
 35. The invention of claims 23 or 24wherein one of said circuits is an equalizer which has as first andsecond ones of its operating modes the setting of the coefficients ofsaid equalizer to first and second initial sets of values, respectively.36. The invention of claims 23 or 24 wherein one of said circuits is anequalizer which has as one of its operating modes the updating of itscoefficients in response to ideal reference data and as another of itsoperating modes the updating of said coefficients in response to datadecisions made by said receiver means.
 37. The invention of claims 23 or24 wherein one of said circuits is an equalizer which has a normaloperating mode, a start-up mode, and a retrain mode.
 38. The inventionof claim 24 wherein at least one of said transmitter and receiver meansoperates at least in part in response to a predetermined set of storedprogram instructions and wherein said initialization means is furtheroperative for providing said program instructions to said one of saidtransmitter and receiver means.
 39. The invention of claim 24 wherein atleast one of said transmitter and receiver means is adapted to operatein accordance with a plurality of alternative signal processing formatsand wherein said initialization means is further operative forspecifying initial ones of said formats.
 40. The invention of claim 39wherein said plurality of signal processing formats includes scramblingformats, differential encoding formats and modulation formats.
 41. Theinvention of claim 39 wherein said plurality of signal processingformats includes descrambling and differential decoding formats.
 42. Theinvention of claim 41 wherein said plurality of signal processingformats further includes scrambling formats, differential encodingformats, and modulation formats.
 43. The invention of claims 39, 40 or41 wherein said interrupt service means is adapted to specify at leastone of said signal processing formats to be used during at least one ofsaid start-up operations.
 44. The invention of claim 24 wherein at leastone of said transmitter and receiver means is adapted to operate withalternative values for each of a plurality of operating parameters andwherein said initialization means is further operative for specifyinginitial ones of said parameter values.
 45. The invention of claim 44wherein one of said parameter values is a bit rate.
 46. The invention ofclaim 44 wherein one of said parameter values is a baud rate.
 47. Theinvention of claim 44 wherein one of said parameter values is a carrierfrequency. .Iadd.
 48. A data set for processing data applied to saiddata set to generate transmit data signals representing said data, saiddata set characterized bysignal processing means which includes aplurality of addressable registers, a bus common to said registers, andcontroller means for addressing said registers and for writing into eachregister via said bus at least a first associated information signal,the values of the information signals in said registers specifying themanner in which said data are to be processed, said signal processingmeans further including circuit means distinct from said controllermeans for processing said data in accordance with said informationsignal values to generate said transmit data signals, and means forapplying said transmit data signals to a transmission line. .Iaddend..Iadd.49. The invention of claim 48 wherein at least ones of saidinformation signals specify operating modes for said signal processingmeans. .Iaddend. .Iadd.50. The invention of claim 48 wherein at leastones of said information signals specify operating parameter values forsaid signal processing means. .Iaddend. .Iadd.51. The invention of claim48 wherein at least ones of said information signals specify signalprocessing formats for said signal processing means. .Iaddend. .Iadd.52.A data set for processing received data signals applied to said data setto recover far-end data characterized by signal processing means whichincludes a plurality of addressable registers, a bus common to saidregisters, and controller means for addressing said registers and forwriting into each register via said bus at least a first associatedinformation signal, the values of the information signals in saidregisters specifying the manner in which said received data signals areto be processed, said signal processing means further including circuitmeans distinct from said controller means for processing said receiveddata signals in accordance with said information signal values torecover said far-end data. .Iaddend. .Iadd.53. The invention of claim 52wherein at least ones of said information signals specify operatingmodes for said signal processing means. .Iaddend. .Iadd.54. Theinvention of claim 52 wherein at least ones of said information signalsspecify operating parameter values for said signal processing means..Iaddend. .Iadd.55. The invention of claim 52 wherein at least ones ofsaid information signals specify signal processing formats for saidsignal processing means. .Iaddend. .Iadd.56. A data set for processingdata applied to said data set to generate transmit data signalsrepresenting said data, and processing received data signals applied tosaid data set to recover far-end data characterized bysignal processingmeans which includes a first plurality of addressable registers and asecond plurality of addressable registers, a bus common to said firstand second pluralities of addressable registers, and controller meansfor addressing said registers and for writing into each register viasaid bus at least a first associated information signal, the values ofthe information signals in said first plurality registers specifying themanner in which said data are to be processed and the values of theinformation signals in said second plurality registers specifying themanner in which said received data signals are to be processed, saidsignal processing means further including circuit means distinct fromsaid controller means for processing said data in accordance with theinformation signal values in said first plurality registers to generatesaid transmit data signals and for processing said received data signalsin accordance with the information signal values in said secondplurality registers to recover said far-end data, and means for applyingsaid transmit data signals to a transmisson line. .Iaddend. .Iadd.57.The invention of claim 56 wherein at least ones of said informationsignals specify operating modes for said signal processing means..Iaddend. .Iadd.58. The invention of claim 56 wherein at least ones ofsaid information signals specify operating parameter values for saidsignal processing means. .Iaddend. .Iadd.59. The invention of claim 56wherein at least ones of said information signals specify signalprocessing formats for said signal processing means. .Iaddend. .Iadd.60.A data set comprisingsignal processing means including means forencoding user-provided data in accordance with at least a specified oneof a plurality of predetermined encoding formats and means for applyingto a transmission channel a transmit data signal representing theencoded data, said signal processing means further including a pluralityof registers, a bus common to said registers, and astored-program-controlled processor distinct from said signal processingmeans and including means for writing information signals into ones ofsaid registers via said bus, ones of said information signals specifyingto said signal processing means said at least one format. .Iaddend..Iadd.61. A data set comprising signal processing means including meansfor receiving a data signal from a transmission channel, said datasignal representing encoded data, and means for decoding the receivedsignal in accordance with at least a specified one of a plurality ofpredetermined decoding formats, said signal processing means furtherincluding a plurality of registers, a bus common to said registers, anda stored-program-controlled processor distinct from said signalprocessing means and including means for writing information signalsinto ones of said registers via said bus, ones of said informationsignals specifying to said signal processing means said at least one ofsaid decoding formats. .Iaddend.